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revision 1764, Wed Dec 6 19:55:07 2006 UTC revision 1821, Fri Nov 28 18:16:42 2008 UTC
# Line 19  Line 19 
19   *  along with this program ; if not, write to the Free Software   *  along with this program ; if not, write to the Free Software
20   *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA   *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21   *   *
22   * $Id: xvid.h,v 1.60 2006-12-06 19:55:07 Isibaar Exp $   * $Id: xvid.h,v 1.64 2008-11-28 18:16:42 Isibaar Exp $
23   *   *
24   ****************************************************************************/   ****************************************************************************/
25    
# Line 57  Line 57 
57  #define XVID_API_MAJOR(a)        (((a)>>16) & 0xff)  #define XVID_API_MAJOR(a)        (((a)>>16) & 0xff)
58  #define XVID_API_MINOR(a)        (((a)>> 0) & 0xff)  #define XVID_API_MINOR(a)        (((a)>> 0) & 0xff)
59    
60  #define XVID_VERSION             XVID_MAKE_VERSION(1,2,-127)  #define XVID_VERSION             XVID_MAKE_VERSION(1,3,-127)
61  #define XVID_API                 XVID_MAKE_API(4, 1)  #define XVID_API                 XVID_MAKE_API(4, 3)
62    
63  #define XVID_UNSTABLE  #define XVID_UNSTABLE
64    
# Line 73  Line 73 
73   * doesnt hurt but not increasing it could cause difficulty for decoders in the   * doesnt hurt but not increasing it could cause difficulty for decoders in the
74   * future   * future
75   */   */
76  #define XVID_BS_VERSION 47  #define XVID_BS_VERSION 55
77    
78  /*****************************************************************************  /*****************************************************************************
79   * error codes   * error codes
# Line 171  Line 171 
171  #define XVID_CPU_SSE      (1<< 2) /*       sse : pentium3, athlonXP */  #define XVID_CPU_SSE      (1<< 2) /*       sse : pentium3, athlonXP */
172  #define XVID_CPU_SSE2     (1<< 3) /*      sse2 : pentium4, athlon64 */  #define XVID_CPU_SSE2     (1<< 3) /*      sse2 : pentium4, athlon64 */
173  #define XVID_CPU_SSE3     (1<< 8) /*      sse3 : pentium4, athlon64 */  #define XVID_CPU_SSE3     (1<< 8) /*      sse3 : pentium4, athlon64 */
174    #define XVID_CPU_SSE41    (1<< 9) /*      sse41: penryn */
175  #define XVID_CPU_3DNOW    (1<< 4) /*     3dnow : k6-2 */  #define XVID_CPU_3DNOW    (1<< 4) /*     3dnow : k6-2 */
176  #define XVID_CPU_3DNOWEXT (1<< 5) /* 3dnow-ext : athlon */  #define XVID_CPU_3DNOWEXT (1<< 5) /* 3dnow-ext : athlon */
177  #define XVID_CPU_TSC      (1<< 6) /*       tsc : Pentium */  #define XVID_CPU_TSC      (1<< 6) /*       tsc : Pentium */
# Line 554  Line 555 
555          /*accuracy 0 very accurate 4 very fast*/          /*accuracy 0 very accurate 4 very fast*/
556          int acc;          int acc;
557    
558        int cpu_flags; /* XVID_CPU_XXX flags */
559    
560  } xvid_plugin_ssim_t;  } xvid_plugin_ssim_t;
561    
562  /*****************************************************************************  /*****************************************************************************
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