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revision 281, Wed Jul 10 14:24:56 2002 UTC revision 282, Wed Jul 10 14:26:02 2002 UTC
# Line 16  Line 16 
16  c13 = f45  c13 = f45
17  c14 = f46  c14 = f46
18  c15 = f47  c15 = f47
   
19  .sdata  .sdata
20  .align 16  .align 16
21  .data_c0:  .data_c0:
# Line 60  Line 59 
59  .single 1.000000000000000000000000000000, 1.000000000000000000000000000000  .single 1.000000000000000000000000000000, 1.000000000000000000000000000000
60    
61  .text  .text
62  .global idct_ia64, idct_ia64_init  .global idct_ia64
63    .global idct_ia64_init
64  .align 16  .align 16
65  .proc idct_ia64_init  .proc idct_ia64_init
66  idct_ia64_init:  idct_ia64_init:
67          br.ret.sptk.few b0          br.ret.sptk.few b0
68  .endp  .endp
   
69  .align 16  .align 16
70  .proc idct_ia64  .proc idct_ia64
71  idct_ia64:  idct_ia64:
# Line 1512  Line 1510 
1510          ;;          ;;
1511          st4   [addreg1] = r33, 8          st4   [addreg1] = r33, 8
1512          st4   [addreg2] = r34, 8          st4   [addreg2] = r34, 8
1513            ;;
1514          st4   [addreg1] = r35, 8          st4   [addreg1] = r35, 8
1515          st4   [addreg2] = r36, 8          st4   [addreg2] = r36, 8
1516            ;;
1517          st4   [addreg1] = r37, 8          st4   [addreg1] = r37, 8
1518          st4   [addreg2] = r38, 8          st4   [addreg2] = r38, 8
1519            ;;
1520          st4   [addreg1] = r39, 8          st4   [addreg1] = r39, 8
1521          st4   [addreg2] = r40, 8          st4   [addreg2] = r40, 8
1522            ;;
1523          st4   [addreg1] = r41, 8          st4   [addreg1] = r41, 8
1524          st4   [addreg2] = r42, 8          st4   [addreg2] = r42, 8
1525            ;;
1526          st4   [addreg1] = r43, 8          st4   [addreg1] = r43, 8
1527          st4   [addreg2] = r44, 8          st4   [addreg2] = r44, 8
1528            ;;
1529          st4   [addreg1] = r45, 8          st4   [addreg1] = r45, 8
1530          st4   [addreg2] = r46, 8          st4   [addreg2] = r46, 8
1531            ;;
1532          st4   [addreg1] = r47, 8          st4   [addreg1] = r47, 8
1533          st4   [addreg2] = r48, 8          st4   [addreg2] = r48, 8
1534            ;;
1535          st4   [addreg1] = r49, 8          st4   [addreg1] = r49, 8
1536          st4   [addreg2] = r50, 8          st4   [addreg2] = r50, 8
1537            ;;
1538          st4   [addreg1] = r51, 8          st4   [addreg1] = r51, 8
1539          st4   [addreg2] = r52, 8          st4   [addreg2] = r52, 8
1540            ;;
1541          st4   [addreg1] = r53, 8          st4   [addreg1] = r53, 8
1542          st4   [addreg2] = r54, 8          st4   [addreg2] = r54, 8
1543            ;;
1544          st4   [addreg1] = r55, 8          st4   [addreg1] = r55, 8
1545          st4   [addreg2] = r56, 8          st4   [addreg2] = r56, 8
1546            ;;
1547          st4   [addreg1] = r57, 8          st4   [addreg1] = r57, 8
1548          st4   [addreg2] = r58, 8          st4   [addreg2] = r58, 8
1549            ;;
1550          st4   [addreg1] = r59, 8          st4   [addreg1] = r59, 8
1551          st4   [addreg2] = r60, 8          st4   [addreg2] = r60, 8
1552            ;;
1553          st4   [addreg1] = r61, 8          st4   [addreg1] = r61, 8
1554          st4   [addreg2] = r62, 8          st4   [addreg2] = r62, 8
1555            ;;
1556          st4   [addreg1] = r63, 8          st4   [addreg1] = r63, 8
1557          st4   [addreg2] = r64, 8          st4   [addreg2] = r64, 8
1558            ;;
1559    
1560          mov     ar.pfs = r16          mov     ar.pfs = r16
1561          br.ret.sptk.few b0          br.ret.sptk.few b0
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