23 |
* |
* |
24 |
* History: |
* History: |
25 |
* |
* |
26 |
|
* 17.04.2002 re-enabled lumi masking in 1st pass |
27 |
|
* 15.04.2002 updated cbr support |
28 |
* 07.04.2002 min keyframe interval checkbox |
* 07.04.2002 min keyframe interval checkbox |
29 |
* 2-pass max bitrate and overflow customization |
* 2-pass max bitrate and overflow customization |
30 |
* 04.04.2002 interlacing support |
* 04.04.2002 interlacing support |
70 |
|
|
71 |
REG_INT const reg_ints[] = { |
REG_INT const reg_ints[] = { |
72 |
{"mode", ®.mode, DLG_MODE_CBR}, |
{"mode", ®.mode, DLG_MODE_CBR}, |
|
{"bitrate", ®.bitrate, 900000}, |
|
73 |
{"quality", ®.quality, 85}, |
{"quality", ®.quality, 85}, |
74 |
{"quant", ®.quant, 5}, |
{"quant", ®.quant, 5}, |
75 |
{"rc_buffersize", ®.rc_buffersize, 16}, |
{"rc_bitrate", ®.rc_bitrate, 900000}, |
76 |
|
{"rc_reaction_delay_factor",®.rc_reaction_delay_factor, 16}, |
77 |
|
{"rc_averaging_period", ®.rc_averaging_period, 100}, |
78 |
|
{"rc_buffer", ®.rc_buffer, 100}, |
79 |
|
|
80 |
{"motion_search", ®.motion_search, 5}, |
{"motion_search", ®.motion_search, 5}, |
81 |
{"quant_type", ®.quant_type, 0}, |
{"quant_type", ®.quant_type, 0}, |
292 |
{ |
{ |
293 |
default : |
default : |
294 |
case DLG_MODE_CBR : |
case DLG_MODE_CBR : |
295 |
config->bitrate = config_get_int(hDlg, IDC_VALUE, config->bitrate) * CONFIG_KBPS; |
config->rc_bitrate = config_get_int(hDlg, IDC_VALUE, config->rc_bitrate) * CONFIG_KBPS; |
296 |
break; |
break; |
297 |
|
|
298 |
case DLG_MODE_VBR_QUAL : |
case DLG_MODE_VBR_QUAL : |
309 |
} |
} |
310 |
|
|
311 |
config->mode = SendDlgItemMessage(hDlg, IDC_MODE, CB_GETCURSEL, 0, 0); |
config->mode = SendDlgItemMessage(hDlg, IDC_MODE, CB_GETCURSEL, 0, 0); |
|
config->rc_buffersize = config_get_int(hDlg, IDC_CBRBUFFER, config->rc_buffersize); |
|
312 |
} |
} |
313 |
|
|
314 |
|
|
327 |
|
|
328 |
case DLG_MODE_CBR : |
case DLG_MODE_CBR : |
329 |
text = "Bitrate (Kbps):"; |
text = "Bitrate (Kbps):"; |
330 |
value = config->bitrate / CONFIG_KBPS; |
value = config->rc_bitrate / CONFIG_KBPS; |
331 |
break; |
break; |
332 |
|
|
333 |
case DLG_MODE_VBR_QUAL : |
case DLG_MODE_VBR_QUAL : |
351 |
|
|
352 |
EnableWindow(GetDlgItem(hDlg, IDC_VALUE_STATIC), enabled); |
EnableWindow(GetDlgItem(hDlg, IDC_VALUE_STATIC), enabled); |
353 |
EnableWindow(GetDlgItem(hDlg, IDC_VALUE), enabled); |
EnableWindow(GetDlgItem(hDlg, IDC_VALUE), enabled); |
|
EnableWindow(GetDlgItem(hDlg, IDC_CBRBUFFER_STATIC), (config->mode == DLG_MODE_CBR)); |
|
|
EnableWindow(GetDlgItem(hDlg, IDC_CBRBUFFER), (config->mode == DLG_MODE_CBR)); |
|
354 |
} |
} |
355 |
|
|
356 |
|
|
371 |
case DLG_MODE_CBR : |
case DLG_MODE_CBR : |
372 |
text = "Bitrate (Kbps):"; |
text = "Bitrate (Kbps):"; |
373 |
range = MAKELONG(0,10000); |
range = MAKELONG(0,10000); |
374 |
pos = config->bitrate / CONFIG_KBPS; |
pos = config->rc_bitrate / CONFIG_KBPS; |
375 |
break; |
break; |
376 |
|
|
377 |
case DLG_MODE_VBR_QUAL : |
case DLG_MODE_VBR_QUAL : |
470 |
}; |
}; |
471 |
|
|
472 |
const int qual_disable[] = { |
const int qual_disable[] = { |
473 |
|
IDC_CBR_REACTIONDELAY, IDC_CBR_AVERAGINGPERIOD, IDC_CBR_BUFFER, |
474 |
IDC_KFBOOST, IDC_DISCARD1PASS, IDC_DUMMY2PASS, |
IDC_KFBOOST, IDC_DISCARD1PASS, IDC_DUMMY2PASS, |
475 |
IDC_CURVECOMPH, IDC_CURVECOMPL, IDC_PAYBACK, IDC_PAYBACKBIAS, IDC_PAYBACKPROP, |
IDC_CURVECOMPH, IDC_CURVECOMPL, IDC_PAYBACK, IDC_PAYBACKBIAS, IDC_PAYBACKPROP, |
476 |
IDC_STATS1, IDC_STATS1_BROWSE, IDC_STATS2, IDC_STATS2_BROWSE, |
IDC_STATS1, IDC_STATS1_BROWSE, IDC_STATS2, IDC_STATS2_BROWSE, |
478 |
}; |
}; |
479 |
|
|
480 |
const int quant_disable[] = { |
const int quant_disable[] = { |
481 |
|
IDC_CBR_REACTIONDELAY, IDC_CBR_AVERAGINGPERIOD, IDC_CBR_BUFFER, |
482 |
IDC_MINIQUANT, IDC_MAXIQUANT, IDC_MINPQUANT, IDC_MAXPQUANT, |
IDC_MINIQUANT, IDC_MAXIQUANT, IDC_MINPQUANT, IDC_MAXPQUANT, |
483 |
IDC_KFBOOST, IDC_DISCARD1PASS, IDC_DUMMY2PASS, |
IDC_KFBOOST, IDC_DISCARD1PASS, IDC_DUMMY2PASS, |
484 |
IDC_CURVECOMPH, IDC_CURVECOMPL, IDC_PAYBACK, IDC_PAYBACKBIAS, IDC_PAYBACKPROP, |
IDC_CURVECOMPH, IDC_CURVECOMPL, IDC_PAYBACK, IDC_PAYBACKBIAS, IDC_PAYBACKPROP, |
487 |
}; |
}; |
488 |
|
|
489 |
const int twopass1_disable[] = { |
const int twopass1_disable[] = { |
490 |
IDC_LUMMASK, IDC_MINIQUANT, IDC_MAXIQUANT, IDC_MINPQUANT, IDC_MAXPQUANT, |
IDC_CBR_REACTIONDELAY, IDC_CBR_AVERAGINGPERIOD, IDC_CBR_BUFFER, |
491 |
|
IDC_MINIQUANT, IDC_MAXIQUANT, IDC_MINPQUANT, IDC_MAXPQUANT, |
492 |
IDC_KFBOOST, IDC_DUMMY2PASS, |
IDC_KFBOOST, IDC_DUMMY2PASS, |
493 |
IDC_CURVECOMPH, IDC_CURVECOMPL, IDC_PAYBACK, IDC_PAYBACKBIAS, IDC_PAYBACKPROP, |
IDC_CURVECOMPH, IDC_CURVECOMPL, IDC_PAYBACK, IDC_PAYBACKBIAS, IDC_PAYBACKPROP, |
494 |
IDC_STATS2, IDC_STATS2_BROWSE, |
IDC_STATS2, IDC_STATS2_BROWSE, |
497 |
}; |
}; |
498 |
|
|
499 |
const int twopass2_ext_disable[] = { |
const int twopass2_ext_disable[] = { |
500 |
|
IDC_CBR_REACTIONDELAY, IDC_CBR_AVERAGINGPERIOD, IDC_CBR_BUFFER, |
501 |
IDC_CREDITS_RATE_RADIO, IDC_CREDITS_QUANT_RADIO, IDC_CREDITS_QUANT_STATIC, |
IDC_CREDITS_RATE_RADIO, IDC_CREDITS_QUANT_RADIO, IDC_CREDITS_QUANT_STATIC, |
502 |
IDC_CREDITS_SIZE_RADIO, IDC_CREDITS_END_STATIC, IDC_CREDITS_RATE, |
IDC_CREDITS_SIZE_RADIO, IDC_CREDITS_END_STATIC, IDC_CREDITS_RATE, |
503 |
IDC_CREDITS_QUANTI, IDC_CREDITS_QUANTP, IDC_CREDITS_START_SIZE, IDC_CREDITS_END_SIZE |
IDC_CREDITS_QUANTI, IDC_CREDITS_QUANTP, IDC_CREDITS_START_SIZE, IDC_CREDITS_END_SIZE |
504 |
}; |
}; |
505 |
|
|
506 |
const int twopass2_int_disable[] = { |
const int twopass2_int_disable[] = { |
507 |
|
IDC_CBR_REACTIONDELAY, IDC_CBR_AVERAGINGPERIOD, IDC_CBR_BUFFER, |
508 |
IDC_STATS2, IDC_STATS2_BROWSE |
IDC_STATS2, IDC_STATS2_BROWSE |
509 |
}; |
}; |
510 |
|
|
660 |
|
|
661 |
CheckRadioButton(hDlg, IDC_CPU_AUTO, IDC_CPU_FORCE, |
CheckRadioButton(hDlg, IDC_CPU_AUTO, IDC_CPU_FORCE, |
662 |
config->cpu & XVID_CPU_FORCE ? IDC_CPU_FORCE : IDC_CPU_AUTO ); |
config->cpu & XVID_CPU_FORCE ? IDC_CPU_FORCE : IDC_CPU_AUTO ); |
663 |
|
|
664 |
|
SetDlgItemInt(hDlg, IDC_CBR_REACTIONDELAY, config->rc_reaction_delay_factor, FALSE); |
665 |
|
SetDlgItemInt(hDlg, IDC_CBR_AVERAGINGPERIOD, config->rc_averaging_period, FALSE); |
666 |
|
SetDlgItemInt(hDlg, IDC_CBR_BUFFER, config->rc_buffer, FALSE); |
667 |
break; |
break; |
668 |
} |
} |
669 |
} |
} |
798 |
config->cpu |= ISDLGSET(IDC_CPU_3DNOW) ? XVID_CPU_3DNOW: 0; |
config->cpu |= ISDLGSET(IDC_CPU_3DNOW) ? XVID_CPU_3DNOW: 0; |
799 |
config->cpu |= ISDLGSET(IDC_CPU_3DNOWEXT) ? XVID_CPU_3DNOWEXT: 0; |
config->cpu |= ISDLGSET(IDC_CPU_3DNOWEXT) ? XVID_CPU_3DNOWEXT: 0; |
800 |
config->cpu |= ISDLGSET(IDC_CPU_FORCE) ? XVID_CPU_FORCE : 0; |
config->cpu |= ISDLGSET(IDC_CPU_FORCE) ? XVID_CPU_FORCE : 0; |
801 |
|
|
802 |
|
config->rc_reaction_delay_factor = config_get_int(hDlg, IDC_CBR_REACTIONDELAY, config->rc_reaction_delay_factor); |
803 |
|
config->rc_averaging_period = config_get_int(hDlg, IDC_CBR_AVERAGINGPERIOD, config->rc_averaging_period); |
804 |
|
config->rc_buffer = config_get_int(hDlg, IDC_CBR_BUFFER, config->rc_buffer); |
805 |
break; |
break; |
806 |
} |
} |
807 |
} |
} |
883 |
SendDlgItemMessage(hDlg, IDC_MODE, CB_ADDSTRING, 0, (LPARAM)"Null - test speed"); |
SendDlgItemMessage(hDlg, IDC_MODE, CB_ADDSTRING, 0, (LPARAM)"Null - test speed"); |
884 |
|
|
885 |
SendDlgItemMessage(hDlg, IDC_MODE, CB_SETCURSEL, config->mode, 0); |
SendDlgItemMessage(hDlg, IDC_MODE, CB_SETCURSEL, config->mode, 0); |
|
SetDlgItemInt(hDlg, IDC_CBRBUFFER, config->rc_buffersize, FALSE); |
|
886 |
|
|
887 |
InitCommonControls(); |
InitCommonControls(); |
888 |
|
|
933 |
config_reg_default(config); |
config_reg_default(config); |
934 |
|
|
935 |
SendDlgItemMessage(hDlg, IDC_MODE, CB_SETCURSEL, config->mode, 0); |
SendDlgItemMessage(hDlg, IDC_MODE, CB_SETCURSEL, config->mode, 0); |
|
SetDlgItemInt(hDlg, IDC_CBRBUFFER, config->rc_buffersize, FALSE); |
|
936 |
|
|
937 |
main_slider(hDlg, config); |
main_slider(hDlg, config); |
938 |
main_value(hDlg, config); |
main_value(hDlg, config); |