1 |
;/************************************************************************** |
;/**************************************************************************** |
2 |
; * |
; * |
3 |
; * XVID MPEG-4 VIDEO CODEC |
; * XVID MPEG-4 VIDEO CODEC |
4 |
; * sse2 sum of absolute difference |
; * - SSE2 optimized SAD operators - |
5 |
; * |
; * |
6 |
; * This program is free software; you can redistribute it and/or modify |
; * Copyright(C) 2003 Pascal Massimino <skal@planet-d.net> |
7 |
; * it under the terms of the GNU General Public License as published by |
; * |
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; * |
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; * This program is free software; you can redistribute it and/or modify it |
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; * under the terms of the GNU General Public License as published by |
11 |
; * the Free Software Foundation; either version 2 of the License, or |
; * the Free Software Foundation; either version 2 of the License, or |
12 |
; * (at your option) any later version. |
; * (at your option) any later version. |
13 |
; * |
; * |
18 |
; * |
; * |
19 |
; * You should have received a copy of the GNU General Public License |
; * You should have received a copy of the GNU General Public License |
20 |
; * along with this program; if not, write to the Free Software |
; * along with this program; if not, write to the Free Software |
21 |
; * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
; * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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; * |
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; *************************************************************************/ |
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;/************************************************************************** |
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; * |
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; * History: |
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; * |
; * |
23 |
; * 24.05.2002 inital version; (c)2002 Dmitry Rozhdestvensky |
; * $Id: sad_sse2.asm,v 1.9 2004-03-22 22:36:24 edgomez Exp $ |
24 |
; * |
; * |
25 |
; *************************************************************************/ |
; ***************************************************************************/ |
26 |
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27 |
bits 32 |
BITS 32 |
28 |
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29 |
%macro cglobal 1 |
%macro cglobal 1 |
30 |
%ifdef PREFIX |
%ifdef PREFIX |
35 |
%endif |
%endif |
36 |
%endmacro |
%endmacro |
37 |
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38 |
%define sad_debug 0 ;1=unaligned 2=ref unaligned 3=aligned 0=autodetect |
;============================================================================= |
39 |
%define dev_debug 2 ;1=unaligned 2=aligned 0=autodetect |
; Read only data |
40 |
%define test_stride_alignment 0 ;test stride for alignment while autodetect |
;============================================================================= |
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%define early_return 0 ;use early return in sad |
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41 |
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42 |
section .data |
%ifdef FORMAT_COFF |
43 |
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SECTION .rodata data |
44 |
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%else |
45 |
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SECTION .rodata data align=16 |
46 |
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%endif |
47 |
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48 |
align 64 |
ALIGN 64 |
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buffer times 4*8 dd 0 ;8 128-bit words |
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49 |
zero times 4 dd 0 |
zero times 4 dd 0 |
50 |
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51 |
section .text |
;============================================================================= |
52 |
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; Code |
53 |
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;============================================================================= |
54 |
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55 |
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SECTION .text |
56 |
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57 |
cglobal sad16_sse2 |
cglobal sad16_sse2 |
58 |
cglobal dev16_sse2 |
cglobal dev16_sse2 |
59 |
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60 |
;=========================================================================== |
;----------------------------------------------------------------------------- |
61 |
; General macros for SSE2 code |
; uint32_t sad16_sse2 (const uint8_t * const cur, <- assumed aligned! |
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;=========================================================================== |
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%macro load_stride 1 |
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mov ecx,%1 |
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add ecx,ecx |
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mov edx,ecx |
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add ecx,%1 ;stride*3 |
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add edx,edx ;stride*4 |
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%endmacro |
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%macro sad8lines 1 |
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psadbw xmm0,[%1] |
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psadbw xmm1,[%1+ebx] |
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psadbw xmm2,[%1+ebx*2] |
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psadbw xmm3,[%1+ecx] |
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add %1,edx |
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psadbw xmm4,[%1] |
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psadbw xmm5,[%1+ebx] |
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psadbw xmm6,[%1+ebx*2] |
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psadbw xmm7,[%1+ecx] |
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add %1,edx |
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%endmacro |
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%macro after_sad 1 ; Summarizes 0th and 4th words of all xmm registers |
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paddusw xmm0,xmm1 |
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paddusw xmm2,xmm3 |
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paddusw xmm4,xmm5 |
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paddusw xmm6,xmm7 |
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paddusw xmm0,xmm2 |
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paddusw xmm4,xmm6 |
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paddusw xmm4,xmm0 |
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pshufd xmm5,xmm4,11111110b |
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paddusw xmm5,xmm4 |
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pextrw %1,xmm5,0 ;less latency then movd |
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%endmacro |
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%macro restore 1 ;restores used registers |
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%if %1=1 |
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pop ebp |
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%endif |
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pop edi |
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pop esi |
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pop ebx |
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%endmacro |
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;=========================================================================== |
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; |
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; uint32_t sad16_sse2 (const uint8_t * const cur, |
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62 |
; const uint8_t * const ref, |
; const uint8_t * const ref, |
63 |
; const uint32_t stride, |
; const uint32_t stride, |
64 |
; const uint32_t best_sad); |
; const uint32_t /*ignored*/); |
65 |
; |
;----------------------------------------------------------------------------- |
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; |
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;=========================================================================== |
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align 16 |
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sad16_sse2 |
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push ebx |
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push esi |
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push edi |
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mov ebx,[esp + 3*4 + 12] ;stride |
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%if sad_debug<>0 |
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mov edi,[esp + 3*4 + 4] |
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cglobal sad16_sse2 |
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mov esi,[esp + 3*4 + 8] |
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%endif |
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%if sad_debug=1 |
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jmp sad16_sse2_ul |
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%endif |
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%if sad_debug=2 |
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jmp sad16_sse2_semial |
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%endif |
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%if sad_debug=3 |
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jmp sad16_sse2_al |
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%endif |
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%if test_stride_alignment<>0 |
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test ebx,15 |
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jnz sad16_sse2_ul |
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%endif |
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mov edi,[esp + 3*4 + 4] ;cur (most likely aligned) |
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66 |
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test edi,15 |
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cmovz esi,[esp + 3*4 + 8] ;load esi if edi is aligned |
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cmovnz esi,edi ;move to esi and load edi |
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cmovnz edi,[esp + 3*4 + 8] ;if not |
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jnz esi_unaligned |
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test esi,15 |
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jnz near sad16_sse2_semial |
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jmp sad16_sse2_al |
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esi_unaligned: test edi,15 |
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jnz near sad16_sse2_ul |
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jmp sad16_sse2_semial |
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;=========================================================================== |
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; Branch requires 16-byte alignment of esi and edi and stride |
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;=========================================================================== |
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%macro sad16x8_al 1 |
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movdqa xmm0,[esi] |
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movdqa xmm1,[esi+ebx] |
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movdqa xmm2,[esi+ebx*2] |
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movdqa xmm3,[esi+ecx] |
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add esi,edx |
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movdqa xmm4,[esi] |
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movdqa xmm5,[esi+ebx] |
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movdqa xmm6,[esi+ebx*2] |
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movdqa xmm7,[esi+ecx] |
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add esi,edx |
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sad8lines edi |
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after_sad %1 |
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%endmacro |
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align 16 |
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sad16_sse2_al |
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load_stride ebx |
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sad16x8_al eax |
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%if early_return=1 |
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cmp eax,[esp + 3*4 + 16] ;best_sad |
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jg continue_al |
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%endif |
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sad16x8_al ebx |
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add eax,ebx |
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continue_al: restore 0 |
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67 |
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68 |
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%macro SAD_16x16_SSE2 0 |
69 |
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movdqu xmm0, [edx] |
70 |
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movdqu xmm1, [edx+ecx] |
71 |
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lea edx,[edx+2*ecx] |
72 |
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movdqa xmm2, [eax] |
73 |
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movdqa xmm3, [eax+ecx] |
74 |
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lea eax,[eax+2*ecx] |
75 |
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psadbw xmm0, xmm2 |
76 |
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paddusw xmm6,xmm0 |
77 |
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psadbw xmm1, xmm3 |
78 |
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paddusw xmm6,xmm1 |
79 |
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%endmacro |
80 |
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81 |
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ALIGN 16 |
82 |
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sad16_sse2: |
83 |
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mov eax, [esp+ 4] ; cur (assumed aligned) |
84 |
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mov edx, [esp+ 8] ; ref |
85 |
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mov ecx, [esp+12] ; stride |
86 |
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87 |
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pxor xmm6, xmm6 ; accum |
88 |
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89 |
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SAD_16x16_SSE2 |
90 |
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SAD_16x16_SSE2 |
91 |
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SAD_16x16_SSE2 |
92 |
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SAD_16x16_SSE2 |
93 |
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SAD_16x16_SSE2 |
94 |
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SAD_16x16_SSE2 |
95 |
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SAD_16x16_SSE2 |
96 |
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SAD_16x16_SSE2 |
97 |
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98 |
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pshufd xmm5, xmm6, 00000010b |
99 |
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paddusw xmm6, xmm5 |
100 |
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pextrw eax, xmm6, 0 |
101 |
ret |
ret |
102 |
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;=========================================================================== |
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; Branch requires 16-byte alignment of the edi and stride only |
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;=========================================================================== |
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%macro sad16x8_semial 1 |
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movdqu xmm0,[esi] |
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movdqu xmm1,[esi+ebx] |
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movdqu xmm2,[esi+ebx*2] |
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movdqu xmm3,[esi+ecx] |
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add esi,edx |
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movdqu xmm4,[esi] |
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movdqu xmm5,[esi+ebx] |
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movdqu xmm6,[esi+ebx*2] |
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movdqu xmm7,[esi+ecx] |
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add esi,edx |
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sad8lines edi |
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after_sad %1 |
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%endmacro |
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align 16 |
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sad16_sse2_semial |
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load_stride ebx |
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sad16x8_semial eax |
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%if early_return=1 |
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cmp eax,[esp + 3*4 + 16] ;best_sad |
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jg cont_semial |
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%endif |
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sad16x8_semial ebx |
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add eax,ebx |
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cont_semial: restore 0 |
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ret |
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;=========================================================================== |
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; Branch does not require alignment, even stride |
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;=========================================================================== |
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%macro sad16x4_ul 1 |
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movdqu xmm0,[esi] |
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movdqu xmm1,[esi+ebx] |
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movdqu xmm2,[esi+ebx*2] |
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movdqu xmm3,[esi+ecx] |
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add esi,edx |
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movdqu xmm4,[edi] |
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movdqu xmm5,[edi+ebx] |
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movdqu xmm6,[edi+ebx*2] |
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movdqu xmm7,[edi+ecx] |
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add edi,edx |
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psadbw xmm4,xmm0 |
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psadbw xmm5,xmm1 |
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psadbw xmm6,xmm2 |
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psadbw xmm7,xmm3 |
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paddusw xmm4,xmm5 |
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paddusw xmm6,xmm7 |
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paddusw xmm4,xmm6 |
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pshufd xmm7,xmm4,11111110b |
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paddusw xmm7,xmm4 |
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pextrw %1,xmm7,0 |
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%endmacro |
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align 16 |
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sad16_sse2_ul |
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load_stride ebx |
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push ebp |
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sad16x4_ul eax |
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%if early_return=1 |
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cmp eax,[esp + 4*4 + 16] ;best_sad |
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jg continue_ul |
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%endif |
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sad16x4_ul ebp |
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add eax,ebp |
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%if early_return=1 |
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cmp eax,[esp + 4*4 + 16] ;best_sad |
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jg continue_ul |
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%endif |
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sad16x4_ul ebp |
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add eax,ebp |
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%if early_return=1 |
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cmp eax,[esp + 4*4 + 16] ;best_sad |
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jg continue_ul |
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%endif |
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sad16x4_ul ebp |
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add eax,ebp |
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continue_ul: restore 1 |
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ret |
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;=========================================================================== |
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; |
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; uint32_t dev16_sse2(const uint8_t * const cur, |
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; const uint32_t stride); |
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; |
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; experimental! |
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; |
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;=========================================================================== |
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align 16 |
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dev16_sse2 |
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push ebx |
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push esi |
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push edi |
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push ebp |
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mov esi, [esp + 4*4 + 4] ; cur |
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mov ebx, [esp + 4*4 + 8] ; stride |
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cglobal dev16_sse2 |
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mov edi, buffer |
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%if dev_debug=1 |
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jmp dev16_sse2_ul |
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%endif |
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%if dev_debug=2 |
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jmp dev16_sse2_al |
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%endif |
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test esi,15 |
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jnz near dev16_sse2_ul |
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%if test_stride_alignment=1 |
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test ebx,15 |
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jnz dev16_sse2_ul |
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%endif |
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mov edi,esi |
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jmp dev16_sse2_al |
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;=========================================================================== |
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; Branch requires alignment of both the cur and stride |
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;=========================================================================== |
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%macro make_mean 0 |
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add eax,ebp ;mean 16-bit |
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mov al,ah ;eax= {0 0 mean/256 mean/256} |
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mov ebp,eax |
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shl ebp,16 |
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or eax,ebp |
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%endmacro |
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%macro sad_mean16x8_al 3 ;destination,0=zero,1=mean from eax,source |
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%if %2=0 |
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pxor xmm0,xmm0 |
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%else |
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movd xmm0,eax |
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pshufd xmm0,xmm0,0 |
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%endif |
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movdqa xmm1,xmm0 |
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movdqa xmm2,xmm0 |
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movdqa xmm3,xmm0 |
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movdqa xmm4,xmm0 |
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movdqa xmm5,xmm0 |
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movdqa xmm6,xmm0 |
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movdqa xmm7,xmm0 |
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sad8lines %3 |
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after_sad %1 |
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%endmacro |
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align 16 |
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dev16_sse2_al |
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load_stride ebx |
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sad_mean16x8_al eax,0,esi |
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sad_mean16x8_al ebp,0,esi |
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make_mean |
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sad_mean16x8_al ebp,1,edi |
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sad_mean16x8_al eax,1,edi |
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add eax,ebp |
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restore 1 |
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ret |
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;=========================================================================== |
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; Branch does not require alignment |
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;=========================================================================== |
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%macro sad_mean16x8_ul 2 |
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pxor xmm7,xmm7 |
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movdqu xmm0,[%1] |
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movdqu xmm1,[%1+ebx] |
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movdqu xmm2,[%1+ebx*2] |
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movdqu xmm3,[%1+ecx] |
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add %1,edx |
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movdqa [buffer+16*0],xmm0 |
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movdqa [buffer+16*1],xmm1 |
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movdqa [buffer+16*2],xmm2 |
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movdqa [buffer+16*3],xmm3 |
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movdqu xmm4,[%1] |
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movdqu xmm5,[%1+ebx] |
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movdqu xmm6,[%1+ebx*2] |
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movdqa [buffer+16*4],xmm4 |
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movdqa [buffer+16*5],xmm5 |
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movdqa [buffer+16*6],xmm6 |
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103 |
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104 |
|
;----------------------------------------------------------------------------- |
105 |
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; uint32_t dev16_sse2(const uint8_t * const cur, const uint32_t stride); |
106 |
|
;----------------------------------------------------------------------------- |
107 |
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108 |
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%macro MEAN_16x16_SSE2 0 ; eax: src, ecx:stride, mm7: zero or mean => mm6: result |
109 |
|
movdqu xmm0, [eax] |
110 |
|
movdqu xmm1, [eax+ecx] |
111 |
|
lea eax, [eax+2*ecx] ; + 2*stride |
112 |
psadbw xmm0,xmm7 |
psadbw xmm0,xmm7 |
113 |
|
paddusw xmm6, xmm0 |
114 |
psadbw xmm1,xmm7 |
psadbw xmm1,xmm7 |
115 |
psadbw xmm2,xmm7 |
paddusw xmm6, xmm1 |
|
psadbw xmm3,xmm7 |
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psadbw xmm4,xmm7 |
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psadbw xmm5,xmm7 |
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psadbw xmm6,xmm7 |
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movdqu xmm7,[%1+ecx] |
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movdqa [buffer+16*7],xmm7 |
|
|
psadbw xmm7,[zero] |
|
|
|
|
|
add %1,edx |
|
|
|
|
|
after_sad %2 |
|
116 |
%endmacro |
%endmacro |
117 |
|
|
|
align 16 |
|
|
dev16_sse2_ul |
|
|
|
|
|
load_stride ebx |
|
|
|
|
|
sad_mean16x8_ul esi,eax |
|
|
sad_mean16x8_ul esi,ebp |
|
|
|
|
|
make_mean |
|
|
|
|
|
sad_mean16x8_al ebp,1,edi |
|
|
sad_mean16x8_al eax,1,edi |
|
|
|
|
|
add eax,ebp |
|
|
|
|
|
restore 1 |
|
118 |
|
|
119 |
|
ALIGN 16 |
120 |
|
dev16_sse2: |
121 |
|
mov eax, [esp+ 4] ; src |
122 |
|
mov ecx, [esp+ 8] ; stride |
123 |
|
|
124 |
|
pxor xmm6, xmm6 ; accum |
125 |
|
pxor xmm7, xmm7 ; zero |
126 |
|
|
127 |
|
MEAN_16x16_SSE2 |
128 |
|
MEAN_16x16_SSE2 |
129 |
|
MEAN_16x16_SSE2 |
130 |
|
MEAN_16x16_SSE2 |
131 |
|
|
132 |
|
MEAN_16x16_SSE2 |
133 |
|
MEAN_16x16_SSE2 |
134 |
|
MEAN_16x16_SSE2 |
135 |
|
MEAN_16x16_SSE2 |
136 |
|
|
137 |
|
mov eax, [esp+ 4] ; src again |
138 |
|
|
139 |
|
pshufd xmm7, xmm6, 10b |
140 |
|
paddusw xmm7, xmm6 |
141 |
|
pxor xmm6, xmm6 ; zero accum |
142 |
|
psrlw xmm7, 8 ; => Mean |
143 |
|
pshuflw xmm7, xmm7, 0 ; replicate Mean |
144 |
|
packuswb xmm7, xmm7 |
145 |
|
pshufd xmm7, xmm7, 00000000b |
146 |
|
|
147 |
|
MEAN_16x16_SSE2 |
148 |
|
MEAN_16x16_SSE2 |
149 |
|
MEAN_16x16_SSE2 |
150 |
|
MEAN_16x16_SSE2 |
151 |
|
|
152 |
|
MEAN_16x16_SSE2 |
153 |
|
MEAN_16x16_SSE2 |
154 |
|
MEAN_16x16_SSE2 |
155 |
|
MEAN_16x16_SSE2 |
156 |
|
|
157 |
|
pshufd xmm7, xmm6, 10b |
158 |
|
paddusw xmm7, xmm6 |
159 |
|
pextrw eax, xmm7, 0 |
160 |
ret |
ret |