[svn] / branches / dev-api-4 / xvidcore / examples / xvid_bench.c Repository:
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revision 1121, Sun Aug 10 13:10:09 2003 UTC revision 1122, Wed Aug 13 11:44:02 2003 UTC
# Line 19  Line 19 
19   *  along with this program; if not, write to the Free Software   *  along with this program; if not, write to the Free Software
20   *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA   *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
21   *   *
22   * $Id: xvid_bench.c,v 1.9.2.3 2003-06-10 09:14:48 edgomez Exp $   * $Id: xvid_bench.c,v 1.9.2.4 2003-08-13 11:43:45 edgomez Exp $
23   *   *
24   ****************************************************************************/   ****************************************************************************/
25    
# Line 115  Line 115 
115    
116  CPU cpu_list[] =  CPU cpu_list[] =
117  { { "PLAINC", 0 }  { { "PLAINC", 0 }
118    #ifdef ARCH_IS_IA32
119    , { "MMX   ", XVID_CPU_MMX }    , { "MMX   ", XVID_CPU_MMX }
120    , { "MMXEXT", XVID_CPU_MMXEXT | XVID_CPU_MMX }    , { "MMXEXT", XVID_CPU_MMXEXT | XVID_CPU_MMX }
121    , { "SSE2  ", XVID_CPU_SSE2 | XVID_CPU_MMX }    , { "SSE2  ", XVID_CPU_SSE2 | XVID_CPU_MMX }
122    , { "3DNOW ", XVID_CPU_3DNOW }    , { "3DNOW ", XVID_CPU_3DNOW }
123    , { "3DNOWE", XVID_CPU_3DNOWEXT }    , { "3DNOWE", XVID_CPU_3DNOWEXT }
124    #endif
125  //, { "IA64  ", XVID_CPU_IA64 }  //, { "IA64  ", XVID_CPU_IA64 }
126  //, { "TSC   ", XVID_CPU_TSC }  //, { "TSC   ", XVID_CPU_TSC }
127    , { 0, 0 } };    , { 0, 0 } };
128    
129  CPU  cpu_short_list[] =  CPU  cpu_short_list[] =
130  { { "PLAINC", 0 }  { { "PLAINC", 0 }
131    #ifdef ARCH_IS_IA32
132    , { "MMX   ", XVID_CPU_MMX }    , { "MMX   ", XVID_CPU_MMX }
133  //, { "MMXEXT", XVID_CPU_MMXEXT | XVID_CPU_MMX }  //, { "MMXEXT", XVID_CPU_MMXEXT | XVID_CPU_MMX }
134    #endif
135  //, { "IA64  ", XVID_CPU_IA64 }  //, { "IA64  ", XVID_CPU_IA64 }
136    , { 0, 0 } };    , { 0, 0 } };
137    
138  CPU cpu_short_list2[] =  CPU cpu_short_list2[] =
139  { { "PLAINC", 0 }  { { "PLAINC", 0 }
140    #ifdef ARCH_IS_IA32
141    , { "MMX   ", XVID_CPU_MMX }    , { "MMX   ", XVID_CPU_MMX }
142    , { "SSE2  ", XVID_CPU_SSE2 | XVID_CPU_MMX }    , { "SSE2  ", XVID_CPU_SSE2 | XVID_CPU_MMX }
143    #endif
144    , { 0, 0 } };    , { 0, 0 } };
145    
146    
# Line 143  Line 149 
149          int xerr, cpu_type;          int xerr, cpu_type;
150          xvid_gbl_init_t xinit;          xvid_gbl_init_t xinit;
151    
152    #ifdef ARCH_IS_IA32
153          cpu_type = check_cpu_features() & cpu->cpu;          cpu_type = check_cpu_features() & cpu->cpu;
154    #else
155            cpu_type = XVID_CPU_ASM;
156    #endif
157          memset(&xinit, 0, sizeof(xinit));          memset(&xinit, 0, sizeof(xinit));
158          xinit.cpu_flags = cpu_type | XVID_CPU_FORCE;          xinit.cpu_flags = cpu_type | XVID_CPU_FORCE;
159          xinit.version = XVID_VERSION;          xinit.version = XVID_VERSION;
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